The present invention provides a method for fabrication of a contact plug in an embedded memory.
In order to avoid shortcircuiting of devices in an embedded memory, an insulation layer is positioned between each device and circuit. A photo-etching-process (PEP) is then used to form a plurality of contact holes in the insulation layer. A conductive layer fills each contact hole to electrically connect each metal-oxide-semiconductor (MOS) wafer and the circuit.
Please refer to FIG. 1 to FIG. 8. FIG. 1 to FIG. 8 are schematic diagrams of a method of fabricating a landing via and a strip contact in an embedded memory according to the prior art. As shown in FIG. 1, defined on the surface of a silicon substrate 16 of a semiconductor wafer 10 is a memory array region 12 and a periphery circuit region 14. The memory array region 12 comprises at least a cell-well 18, and the periphery circuit region 14 comprises at least an N-well 20 and a P-well 22. In the prior art, a plurality of gates 24, 26, 28 are first formed, separately, in the memory array region 12 and in the periphery circuit region 14. A spacer 30 and a lightly doped drain (LDD) 32 are formed adjacent to each gate 24, 26, 28. As well, a source 34 and a drain 36 are also formed adjacent the gates 26, 28.
As shown in FIG.2, a dielectric layer 38, such as a silicon oxide layer, is then formed on the surface of the semiconductor wafer 10. A photolithographic process is used to define a pattern of several shallow metal connection regions 40 on the surface of the dielectric layer 38, as shown in FIG. 3. Next, another photolithographic process is performed to define a first contact window 44, a second contact window 42, and a third contact window 46 in the dielectric layer 38, as shown in FIG. 4. The first contact window 44 is used to connect to a capacitor, the second contact window 42 subsequently forms a landing via and connects to a bit line, and the third contact window 46 subsequently forms a strip contact and connects to a source or drain in the periphery circuit region 14. The depths of the first contact window 44, the second contact window 42 and the third contact window 46 are all equal, and thus the three contact windows are horizontally aligned.
As shown in FIG. 5, a photolithographic process is then used to form a fourth contact window 48 in the dielectric layer 38. The fourth contact window 48 is used to connect to a gate in the strip contact of the periphery circuit region 14. Since the depth of the fourth contact window 48 is shallower than that of the other contact windows, its horizontal alignment differs to that of the first contact window 44, the second contact window 42 and the third contact window 46. The third contact window 46 and the fourth contact window 48 are separately connected to the gate and source or drain of different transistors, and therefore the two contact windows are located on different vertical planes. As shown in FIG. 6, a barrier layer 50 of titanium nitride and a dielectric layer 52 of tantalum oxide are formed, respectively, on the substrate 16.
As shown in FIG. 7, a photoresist layer (not shown) is used as a mask to etch the dielectric layer 52 so that the dielectric layer 52 remains only in the second contact window 42 and its metal connection region 40. As shown in FIG. 8, a metal layer 54 is deposited on the surface of substrate 16 and fills into each contact window 42, 44, 46, 48 and each metal connection region 40. Finally, the dielectric layer 38 is used as an etching stop layer for chemical mechanical polishing (CMP) of the metal layer 54.
However, in the disclosure of the prior art method for fabricating a landing via and a strip contact of an embedded memory, the landing via and strip contact are fabricated separately due to the large depth difference between the memory array region and the periphery circuit region. Thus, at least four photomasks are needed in the prior art process, leading to a costly and complicated process. As well, the sites used to connect the gate and to connect the source or drain in the strip contact of the periphery circuit region are formed separately, leading to a larger occupation of space of the unit memory.
It is therefore a primary objective of the present invention to provide a fabrication method for a contact plug of an embedded memory, to simplify the complexity and to decrease the cost of the process.
The present method involves first forming a plurality of MOS transistors on a defined memory array region and periphery circuit region of the semiconductor wafer. Then, a first dielectric layer is formed on the memory array region and a plurality of landing pads are also formed in the first dielectric layer. Next, a stop layer and a second dielectric layer are formed on the surface of the semiconductor wafer, and a PEP process is performed to form a plurality of contact plug holes in the second dielectric layer in both the memory array region and the periphery circuit region. Finally, a conductive layer is filled into each hole to simultaneously form each contact plug in both the memory array region and the periphery circuit region.
The present invention method for fabricating contact plugs of an embedded memory require only two photomasks in the process. Moreover, each contact plug and metal interconnection layer of an embedded memory are completed in a single PEP process, thus, simplifying the complexity and decreasing the cost of the process.
These and other objectives of the present invention will no doubt, become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.